Abstrakt

An Efficient Power Reduction in Multiplexer Based On Cordic Using Cadence-Digital IC Design

Uma.P, G.AnuVidhya

CORDIC is an iterative Algorithm to perform a wide range of functions including vector rotations, certain trigonometric, hyperbolic, linear and logarithmic functions. Both non pipelined and 2 level pipelined CORDIC with 8 stages, using two schemes was performed. First scheme was original unrolled CORDIC and second scheme was MUX based pipelined unrolled CORDIC. Compared to first scheme, the second scheme is more reliable, since the second scheme uses multiplexer and registers. By adding multiplexer the area is reduced comparatively to the first architecture, since the first scheme uses only addition, subtraction and shifting operation in all the 8 stages.8 iterations are performed and it is implemented on QUARTUS II software. The same is implemented in cadence tool and the results was compared with QUARTUS II and CADENCE TOOL. An efficient power reduction is obtained in CADENCE (Digital) implementation