Abstrakt

Design of High Speed Vedic Multiplier Using K-Map Boolean Function Techniques

M.Valli, Dr.A.R.Pon Periasamy

This work propose the design of high speed vedic multiplier using the k-map techniques of ancient vedic mathematics that have been modified to improve performance.Vedic multiplier is the ancient system of logic table which has a unique technique of calculations based on truth table.The work has proved the efficiency of vedic method for multiplication which strikes a difference in the actual process of multiplication itself.It enables parallel generation of intermediate products,eliminates unwanted multiplication steps with zeros and scaled to higher bit levels using algorithm with the compatibility to different datatypes.It is most efficient technique giving minimum delay for multiplication of all types of numbers ,either small or large.Further the verilog HDL coding for 32x32 bits multiplication and implementation have been done and output has been displayed.