Abstrakt

Design of Out-Of-Order Superscalar Processor with Speculative Thread Level Parallelism

A.Kamaraj , X.Sharly Monica

The Complexity of handling the complex flow logic has become the major impact in parallel programming. The two main problems associated with the Scheduling of Superscalar Processor are interrupt precision and implementing multiple levels of Branch Prediction. The proposed work implements the Speculative Thread Level parallelism Technique on superscalar Processor, as an alternative source of parallelism which can boost the performance for applications, by overcoming the causes using cache coherence protocols and thus prevent the collision due to dependencies. To address this critical need, a Register transfer level (RTL) model of a superscalar micro architecture have been developed with similar complexity of a current generation processor. The RTL model is written in Verilog and is fully synthesizable. The RTL model is tightly integrated with a C functional simulator to assist and accelerate verification. The dissertation also proposes novel architecture and compiler techniques to efficiently extract speculative parallelism from multiple loop levels.