Abstrakt

Designing Of Fast Multipliers with Ancient Vedic Techniques

Jeevitha.R, Jayanthi.P, Gowthami A.K, Uvarajan K.P

Vedic mathematics is an ancient system of mathematics which performs unique technique of calculations based on 16 sutras. The performance of high speed multiplier is designed based on Urdhva Tiryabhyam, Nikhilam Navatashcaramam Dashatah, and Anurupye algorithms. These algorithms gives minimum delay and used for multiplication of all types of numbers. The performance of high speed multiplier is designed and compared using these sutras for various NxN bit multiplications and implemented on the FFT of the DSP processor. Anurupye Vedic multiplier on FFT is made efficient than Urdhva tiryabhyam and Nikhilam Navatashcaramam Dashatah sutras by more reduction in computation time. Logic verification of these design is verified by simulating the logic circuits in XILINX ISE 9.1 and MODELSIM SE 5.7g using VHDL.