Abstrakt

High Speed 128-bit BCD Adder Architecture Using CLA

J.S.V.Sai Prasanthi, Y.Yamini Devi

Arithmetic and memory address computation are performed using adder operations. Hence, design of adders forms an important subset of electronic chip design functionality. BCD numbers play a prominent role in number system. To perform arithmetic operations on BCD numbers respective circuit has to be designed. To perform BCD addition, BCD adders are used. But the drawback with the BCD adder is low speed in operation due to delay in propagating carry output. This low speed operation will affect the operation of entire system in which it is used. As the technology is advancing day by day there is demand for chips with high speed. So to overcome this drawback, BCD adder using CLA is proposed in this paper. The proposed design is attempted here to reduce the delay and thereby increasing the speed of response. In existing BCD architecture, RCA is used to add numbers. The delay of RCA is high so it is effecting the speed of adder. So in the proposed design, CLA is used instead of RCA and also a parallel prefix network is to be used to produce the carry outputs for all stages. In this paper, a BCD adder using CLA is to be designed for 8, 16, 32, 64 and 128-bit size using VHDL with the help of ISE Xilinx design suite 14.1. The designed adder will be functionally verified by using ISIM simulator. Later, it will be synthesized using XST synthesizer to get the area (in terms of LUTS) and delay(ns). Finally, the designed BCD adders will be compared with conventional BCD adder in terms of delay(ns).