Abstrakt

Stability Analysis of 6T SRAM at 32 Nm Technology

Rajni Sharma , Sanjay Chopade

SRAM area is expected to exceed 90% of overall chip area because of the demand for higher performance, lower power, and higher integration. To increase memory density, memory bitcells are scaled to reduce their area by 50% each technology node. High density SRAM bitcells use the smallest devices in a technology, making SRAM more vulnerable for variations. This variation effect the stability of SRAM. This paper investigates Static random access memory (SRAM) stability in hold/standby, read and write mode. In this paper different techniques to find Static Noise Margin (SNM), Read margin and write margin are discussed. The effect of supply voltage, transistor scaling, word line voltage, threshold voltage, and temperature on SRAM stability is analysis in Standby and Read Mode. From 0.7V to 1.2V the read stability increase 231% and Standby stability increase 135%. When the cell ratio changes from 1 to 3 the stability of SRAM during read mode gets doubled. This paper also investigate the Data Retention Voltage(DRV) during standby and read mode which is the minimum voltage required to hold or read data, any voltage below DRV can flip the state of SRAM. The DRV 6T SRAM in Standby mode is 0.14V and that in read mode is 0.29V.