Abstrakt

Performance Analysis, Designing and Testing 512 Bit Sram Memory Chip Using Xilinx/Modelsim Tool

Monika Solanki

In this thesis a memory chip has been designed with the size of 512 bit using Xilinx or model sim software. Memory Built-in Self-Test (MBIST) or as some refer to it array built-in self-test is an amazing piece of logic. Without any direct connection to the outside world, a very complex embedded memory can be tested efficiently, easily and less costly. Modelling and simulation of MBIST is presented in this paper. The design architecture is written in Very High Speed Integrated Circuit Hardware Description Language (VHDL) code using Xilinx ISE tools. Verification of this architecture is carried out by testing stuck at fault SRAM. A BIST algorithms is implemented like March C- and many more to test the faulty SRAM.